CMOS technology continues to have a trend of finer dimensions with shallower active device volumes. When CMOS technology is used to fabricate an image sensor, then a tradeoff conflict arises as a shrinking active device volume means the quantum efficiency is severely reduced, i.e., the optical sensitivity of an image sensor drops. This trend is most clearly seen when CMOS utilizes silicon on insulator (SOI) wafers with the top silicon layer of the order of 1.0 μm or less in thickness.
Several methods have been described to achieve better quantum efficiency in a CMOS image sensor. U.S. Pat. No. 6,429,036 teaches the use of backside illumination in conjunction with a thinned silicon CMOS image sensor. However, thinning is a difficult operation that has the possibility of a low success rate. U.S. Pat. Nos. 6,501,065; 6,344,368; and 6,344,669 teach the use of an amorphous silicon layer atop the CMOS circuits for the photosensitive element. Amorphous silicon is a challenging material from which to extract photo-generated carriers, since amorphous silicon generally has a high density of trapping sites for the carriers. Suzuki et al. in U.S. Patent application no. 2003/0025160 teach how to combine backside illumination with CMOS circuits in a silicon layer. However, the fabrication requires many instances of non-standard process steps.
The present invention circumvents the difficulties mentioned above and achieves better quantum efficiency with standard CMOS process steps.